High word line voltage (VWL) and a large cell size are typically required to deliver adequate write current (IWrite) with respect to known STT-MRAM on FDSOI designs. However, high VWL and a large cell size can cause time-dependent dielectric breakdown (TDDB) and macro size concerns, respectively. A known solution is to adopt forward body bias (FBB). However, simply adopting FBB can cause unselected cell leakage to increase by an order greater than one (1) and such leakage can affect write-ability (charge-pump) and read-ability (‘1’ and ‘0’ differentiation).
A need therefore exists for methodology enabling formation of a FDSOI STT-MRAM that achieves adequate IWrite with FBB and that minimizes unselected cell leakage current without requiring a large cell size and the resulting device.